1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device, a manufacturing method therefor, a microcomputer with a built-in nonvolatile semiconductor memory device, and a manufacturing method therefor and particularly to the nonvolatile semiconductor memory device excellent in compatibility with the manufacturing process for the microcomputer and the manufacturing method therefor.
2. Description of the Related Art
Recently as a semiconductor memory suitable for high integration (large capacity) while being a nonvolatile memory, a flash memory has been remarkably watched. A memory cell of the flash memory is basically formed by one memory cell transistor having a floating gate, and the threshold of the memory cell transistor is changed by accumulating charges in the floating gate, thereby storing the information to be nonvolatile. Thus, in the flash memory, the memory cell is basically formed by one memory cell transistor only, so that the area occupied by one memory cell is small. This is a major reason why the flash memory is suitable for high integration.
However, as the memory cell transistor is formed by one transistor in the flash memory, it is necessary to adjust the threshold of the memory cell transistor with high accuracy. That is, generally in the flash memory, each memory cell is not provided with a selection transistor, and each memory cell is required to judge whether selected or not from its own threshold voltage, so it is insufficient to simply set the threshold to a high value or a low value according to the information to be stored. For example, in the case of storing one logic level in a memory cell (writing data), the threshold voltage of the memory cell transistor should be set to a voltage equal to or higher than the gate voltage when selected, and in the case of storing the other logic level in the memory cell (erasing data), the threshold voltage of the memory cell transistor should be set to a voltage equal to or lower than the gate voltage when selected and higher than the gate voltage when not selected.
Accordingly, though in writing data, it is not necessary to adjust the threshold with high accuracy, in erasing data, it is necessary to control the threshold with high accuracy to converge the threshold voltage of the memory cell transistor in the above range. Supposing that the threshold voltage in erasing data becomes low to excess to be equal to or lower than the gate voltage when not selected, the memory cell transistor is always in conduction whether selected or not selected to be unreadable, that is, cause the so-called "overerase". Although the flash memory is characterized by batch erasion in block units, a number of memory cells included in each block are not uniform in the erasing characteristic, which has many difficulties in converging the threshold voltage in the above range at the time of erasing a number of memory cells which are batch erased.
Various methods for preventing the above overerase problem have been proposed. One is a method using a split gate type transistor. The split gate type transistor is, so speak, of a memory cell structure in which a selection transistor is integrated with a memory cell transistor. By using such a memory cell structure, even if the memory transistor is in the overerase state, a selection transistor surely secures the non-conducting state of the memory cell when not selected. Thus, it is not necessary to converge the threshold voltage of the memory transistor in erasing in the above range, so that the erasing operation is facilitated.
The split gate type memory cell, however, has the problem that the manufacturing process therefor is complicated. Especially, in the case of integrating it on the same semiconductor substrate as that of a microcomputer or the like, the difficulty in process is caused because the manufacturing process remarkably different from the manufacturing process for the microcomputer or the like is needed.
On the other hand, Japanese Patent Laid-Open No. 7-297304 discloses the technology in which the memory cell is not formed as a split gate type transistor, but formed by two transistors, a separate transistor and a memory transistor to facilitate the manufacturing process. However, according to this technology, the area occupied by one memory cell is remarkably increased. The condition will be described with reference to FIGS. 26 to 30.
FIGS. 26 to 30 are process drawings showing the manufacturing process for a nonvolatile semiconductor memory device according to the technology disclosed in Japanese Patent Laid-Open No. 7-297304.
First, as shown in FIG. 26, a tunnel oxide film 12 and a first polysilicon layer 14 are formed on a semiconductor substrate 10 to form a photo resist 16. Subsequently, as shown in FIG. 27, the first polysilicon layer 14 is selectively subjected to plasma etching with the photo resist 16 as a mask to simultaneously form a gate electrode 20 of a selection transistor S and a floating gate electrode 22 of a memory transistor M. Subsequently, ion implantation is performed with the photo resist 16 and the gate electrodes 20, 22 as a mask to form a source diffusion layer 18 of the selection transistor S, a diffusion layer 24 which is a source diffusion layer of the memory transistor M and also a drain diffusion layer of the selection transistor S, and a drain diffusion layer 26 of the memory transistor M in self-aligning manner.
Subsequently, as shown in FIG. 28, after the photo resist 16 is separated, a poly-poly insulating film (ONO film) 28 is formed, and a second polysilicon film 30 thereon. Subsequently, a photoresist not shown is formed, and plasma etching is performed with the photo resist as a mask to form a control gate electrode 32 of the memory transistor M, as shown in FIG. 29, with the second polysilicon layer left on the floating gate electrode 22 of the memory transistor M. Then, a drain contact 36 is formed in the drain diffusion layer of the memory transistor M. In FIG. 29, the drain contact 36 is shown by its one wall surface only for convenience.
FIG. 30 is a plan view of the thus manufactured memory cell, and FIG. 29 is a sectional view taken along line A--A' of FIG. 30.
According to the method, the manufacturing process for the memory cell is comparatively simple, but the space between the memory transistor M and the selection transistor S needs to be large for a patterning process (FIG. 27) for the floating gate electrode 22 of the memory transistor M and the gate electrode 20 of the selection transistor S and the patterning process (FIG. 29) for the control gate electrode 32 of the memory transistor M. That is, supposing that the film thickness of the second polysilicon layer 30 is 0.15 .mu.m, the gate space between both transistors is needed to be about 0.6 .mu.m in consideration of the fact that a part formed to be the edge of the second polysilicon layer 30 should be flat in patterning. In addition, when a margin (about 0.1 .mu.m on one side) for the irregular stitch is given, a large space as much as about 0.8 .mu.m is needed. Similarly, a large space is needed between the floating gate electrode 22 and the drain contact 36 of the memory transistor. Therefore, the method is not suitable for high integration, and in the case of performing mixed loading with the microcomputer, the microworking technology used in the latest CMOS logic process can not be effectively utilized.
Further, there is the possibility that the patterning remainder 34 of the second polysilicon layer is produced on the side of the gate electrode of the selection transistor S. In the case where the remainder 34 and the control gate electrode 32 are short-circuited, in erasing the memory cell, a large potential difference is locally produced between the gate electrode 20 and the remainder 34 of the selection transistor S, which results in the possibility of breaking the poly-poly insulating film 28. Even if the short-circuit is avoided, there is the possibility that in the course of the manufacturing process, the remainder 34 is separated to cause contamination.